One of the most important parameters in non-volatile memories (NVM) is the current window under read operation biases. In order to ensure reliable and fast access to data stored in non-volatile memory, technology developers and designers try to maximize the current window across entire operating temperature range (e.g., −40° C. to 85° C.), power supply range and process corners. The read current window (IRCW) is defined as the difference between the minimum current conducted by a selected cell in erased state (low voltage threshold (VT)) on one side and a sum of maximum currents conducted by a selected cell in programmed state (high VT) and combined deselected cell currents (bit-line leakage) on the other. The resultant current window (IRCW) is given by the following equation:IRCW=min(Ie+Nm×Idp)−max(Ip+Nm−Ide)≈min(Ie)−max(Ip+Nm×Ide)where Ie is the selected erased cell current, Ip is the selected programmed cell current, Ide is the deselected erased cell current, Idp is the deselected programmed cell current (minimum of Idp is a negligible value), and Nm=N−1 where N is the number of cells per bit-line.
Read current for selected erased and programmed cells as well as deselected cell leakage vary greatly with temperature, so having sufficient current window at one temperature (e.g., at room) does not guarantee a sufficient current window at temperature extremes. In particular, the current leakage through deselected cells increases exponentially with temperature and at high temperatures can exceed the selected erased cell current, forcing the current window to collapse which leads to memory read failure. Furthermore, variations in read current (IRC) with temperature can lead to variations in access time (Ta) required to read the selected cell.
Past attempts to solve these problems in NVM using floating gate or charge-trapping technologies have relied on increased transistor gate lengths and widths, thick dielectric layers between a charge-trapping layer and the transistor channel, or reduced the number of cells per bit-line. However, thicker dielectric layers require larger program-erase voltages, possibly increasing power consumption and impeding integration of the NVM with lower voltage (CMOS) devices. Problems with increasing gate lengths and widths and/or reducing the number of cells per bit-line include limiting the reduction in memory size (or increases in memory density) despite advances in technology, which have enabled the size of active elements in the cell to be reduced to 65 nanometers (nm) and beyond.
Thus, there is a need for an improved memory structure as well as a method of operating the same.